14. Glossary

This glossary provides definitions for terms and abbreviations used in the TF-A documentation.

You can find additional definitions in the Arm Glossary.

AArch32: 32-bit execution state of the ARMv8 ISA
AArch64: 64-bit execution state of the ARMv8 ISA
AMU: Activity Monitor Unit, a hardware monitoring unit introduced by FEAT_AMUv1 that exposes CPU core runtime metrics as a set of counter registers.
API: Application Programming Interface
AT: Address Translation
BTI: Branch Target Identification. An Armv8.5 extension providing additional control flow integrity around indirect branches and their targets.
CoT
COT: Chain of Trust
CSS: Compute Sub-System
CVE: Common Vulnerabilities and Exposures. A CVE document is commonly used to describe a publicly-known security vulnerability.
D-CRTM: Dynamic Code Root of Trust for Measurement
DCE: DRTM Configuration Environment
DICE: Device Identifier Composition Engine
DLME: Dynamically Launched Measured Environment
DPE: DICE Protection Environment
DRTM: Dynamic Root of Trust for Measurement
DS-5: Arm Development Studio 5
DSU: DynamIQ Shared Unit
DT: Device Tree
DTB: Device Tree Blob
EHF: Exception Handling Framework
EL: Exception Level
ERRATA_ABI: Errata management firmware interface
FCONF: Firmware Configuration Framework
FDT: Flattened Device Tree
FF-A: Firmware Framework for Arm A-profile
FIP: Firmware Image Package
FVP: Fixed Virtual Platform
FWU: FirmWare Update
GIC: Generic Interrupt Controller
HES: Arm CCA Hardware Enforced Security
ISA: Instruction Set Architecture
Linaro: A collaborative engineering organization consolidating and optimizing open source software and tools for the Arm architecture.
LSP: A logical secure partition managed by SPM
MMU: Memory Management Unit
MPAM: Memory Partitioning And Monitoring. An optional Armv8.4 extension.
MPIDR: Multiprocessor Affinity Register
MPMM: Maximum Power Mitigation Mechanism, an optional power management mechanism supported by some Arm Armv9-A cores.
MTE: Memory Tagging Extension. An optional Armv8.5 extension that enables hardware-assisted memory tagging.
OEN: Owning Entity Number
OP-TEE: Open Portable Trusted Execution Environment. An example of a TEE
OTE: Open-source Trusted Execution Environment
PAUTH: Pointer Authentication. An optional extension introduced in Armv8.3.
PCR: Platform Configuration Register
PDD: Platform Design Document
PMF: Performance Measurement Framework
PSA: Platform Security Architecture
PSCI: Power State Coordination Interface
PSR: Platform Security Requirements
RAS: Reliability, Availability, and Serviceability extensions. A mandatory extension for the Armv8.2 architecture and later. An optional extension to the base Armv8 architecture.
ROT: Root of Trust
RSE: Runtime Security Engine
SCMI: System Control and Management Interface
SCP: System Control Processor
SDEI: Software Delegated Exception Interface
SDS: Shared Data Storage
SEA: Synchronous External Abort
SiP
SIP: Silicon Provider
SMC: Secure Monitor Call
SMCCC: SMC Calling Convention
SoC: System on Chip
SP: Secure Partition
SPD: Secure Payload Dispatcher
SPM: Secure Partition Manager
SRTM: Static Root of Trust for Measurement
SSBS: Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration bit can be set by software to allow or prevent the hardware from performing speculative operations.
SVE: Scalable Vector Extension
TBB: Trusted Board Boot
TBBR: Trusted Board Boot Requirements
TCB: Trusted Compute Base
TCG: Trusted Computing Group
TEE: Trusted Execution Environment
TF-A: Trusted Firmware-A
TF-M: Trusted Firmware-M
TLB: Translation Lookaside Buffer
TLK: Trusted Little Kernel. A Trusted OS from NVIDIA.
TPM: Trusted Platform Module
TRNG: True Random Number Generator (hardware based)
TSP: Test Secure Payload
TZC: TrustZone Controller
UBSAN: Undefined Behavior Sanitizer
UEFI: Unified Extensible Firmware Interface
WDOG: Watchdog
XLAT: Translation (abbr.). For example, “XLAT table”.